1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus for applying reliability test to semiconductor devices in wafer form and a semiconductor device testing method using the semiconductor device testing apparatus.
2. Description of the Background Art
Inspections for testing reliability of semiconductor devices including the burn-in test. The burn-in test is one of screening methods for selectively rejecting semiconductor devices that might cause initial failures by operating semiconductor devices under severer stress conditions, including higher voltage, higher temperature, etc., than those in actual use.
Conventionally, a burn-in test is conducted in a constant temperature bath with application of given stress after chips that passed a wafer test following the wafer process have been packaged. Nowadays, however, wafer-level burn-in test is also coming into practice, in which a burn-in test is applied to semiconductor devices in wafer form.
FIG. 17 is a conceptual diagram used to describe a conventional wafer-level burn-in test. A wafer to be tested, 101, has a given pattern of a plurality of chips 102 including semiconductor devices to be inspected. The reference numeral 103 denotes a probe card made of ceramic or the like, which has a plurality of probe needles 104. Power supplies and signals for the burn-in test are supplied to the probe card 103 from an external power supply 127 and an external input signal driver device 126 through interconnection cables 128, and they are supplied further to the chips 102 through the probe needles 104. Temperature stress is applied to the chips 102 from a heater (not shown) in a stage 129 on which the tested wafer 101 is set.
In this case, to collectively supply power supplies and signals to all the chips 102 on the tested wafer 101, it is necessary to equip the probe card 103 with the probe needles 104 of a number corresponding to "the total number of the chips 102X the number of terminals per one chip 102". Accordingly, when the chips 102 have an increased number of power-supply terminals and signal terminals, an enormous number of probe needles 104 are required. Then it is difficult to accurately and uniformly bring the probe needles 104 into contact with all terminals.
When the power supplies and signals are sequentially supplied to each chip 102 in a chip-by-chip manner, instead of being collectively supplied to all the chips 102 on the tested wafer 101, the number of probe needles 104 to be provided on the probe card 103 can be reduced, and then the contact characteristic between the probe needles 104 and the power-supply and signal terminals can be improved. However, applying a burn-in test to all the chips 102 by this method requires a time corresponding to "a time required for a burn-in test to one chip 102X the total number of chips 102". This will reduce the throughput and increase the test cost.
FIG. 18 is a plane view showing the structure of a tested wafer 107 that has been improved to solve such problems, and FIG. 19 is a plane view showing the part XIX in FIG. 18 in an enlarged manner. Similarly to the tested wafer 101, the tested wafer 107 has a plurality of chips 102, each chip 102 having a plurality of power-supply terminals and a plurality of signal terminals. When the chips 102 have some of their power-supply terminals and signal terminals to be supplied with the same power supply and the same signals, these power-supply terminals and signal terminals are interconnected through a common interconnection 106 provided on the tested wafer 107. Then these power-supply terminals and signal terminals can be supplied with power supplies and signals not through the probe needles 104 but through the common interconnection 106. Or, the power supplies and signals may be supplied to the chips 102 through BIST (Built In Self Test) circuits 105 fabricated on the tested wafer 107.
However, this conventional semiconductor device testing apparatus requires areas for formation of the common interconnection 106 or the BIST circuits 105 on the tested wafer 107, which reduces the efficiency of product utilization of the tested wafer 107. That is to say, only a reduced number of chips 102 can be formed on one piece of tested wafer 107.
Further, if the BIST circuits 105 do not normally operate due to some trouble in a burn-in test, the burn-in test cannot be performed. Then the reliability cannot be ensured.